In radio frequency transceivers, a frequency synthesizer based on a phase-locked loop (PLL) structure is widely adopted to generate a local oscillation signal, referred to as a local-frequency signal for short, so as to complete frequency shifting of a data signal.
In a wireless communications system, particularly in a wireless terminal, a zero intermediate-frequency (ZIF) radio frequency transceiver architecture is widely adopted in consideration of costs and other factors. In such a radio frequency transceiver architecture, both a signal transmit channel and a signal receive channel require that a frequency of the local-frequency signal be exactly the same as a frequency of a radio frequency carrier signal. In other words, as a local-frequency signal generating apparatus, a frequency synthesizer based on a phase-locked loop has a high enough output frequency precision. For example, for a cellular radio communications system, a frequency step of a radio frequency is 100 kHz. This requires that a phase-locked loop frequency synthesizer applied to such a system be capable of outputting a local-frequency signal at an precision of 100 kHz.
In a wireless communications system, for a phase-locked loop module serving as a frequency synthesizer, a multiplication relationship expressed by the following formula needs to hold between an output radio frequency fRF and an input reference clock frequency fREF:fRF=FCW×fREF 
In the foregoing formula, FCW (Frequency Control Word) is a frequency control word of the phase-locked loop. By FCW value type, that is, a relative relationship between the output radio frequency and the input reference clock frequency, phase-locked loops may be categorized into two types as follows:
(1) Integral frequency-division phase-locked loop. In this type of phase-locked loop, the FCW is a positive integer, which means that the output radio frequency is an integer multiple of the input reference clock frequency. For the foregoing frequency synthesizer requiring a frequency precision of 100 kHz, the input reference clock frequency is required to be fREF=100 kHz.
(2) Fractional frequency-division phase-locked loop. In this type of phase-locked loop, the FCW may have a fractional part. Therefore, an output radio frequency precision of the phase-locked loop may be less than the reference clock frequency. That is, a frequency selection for a reference clock is no longer restricted by the radio frequency precision. Because of advantages in such aspects as locking time, integral phase noise, and design flexibility, the fractional frequency-division phase-locked loop is more widely applied in modern wireless communications systems than the integral frequency-division phase-locked loop.
Additionally, a digital phase-locked loop architecture appearing in recent years transfers phase signal processing of the phase-locked loop to a digital domain, and outputs a high-precision oscillator control signal by using a digital over-sampling technology. In this way, digital design of the phase-locked loop is well implemented. The digital phase-locked loop architecture replaces a traditional phase-locked loop of an analog structure with significant advantages, and has been widely used.
A digital fractional frequency-division phase-locked loop structure widely used at present, shown in FIG. 1, includes the following few basic composition elements:
(1) a time-to-digital converter (TDC), configured to identify a time difference between a reference clock CLK_REF and a feedback clock signal CLK_DIV, and converts this time difference to a digital signal TDC_OUT;
(2) a digital loop filter (DLF), configured to filter a TDC_OUT signal, and output a digital oscillator frequency control signal DLF_OUT;
(3) a digital controlled oscillator (DCO), configured to generate an oscillation signal F_DCO, which is a digital signal;
(4) a feedback frequency divider (DIV), configured to output a frequency division value under control of a Sigma-Delta modulator, perform frequency division processing on the F_DCO by using this frequency division value, and input the signal CLK_DIV that has undergone the frequency division processing to the TDC so as to perform phase discrimination processing on the CLK_REF and the CLK_DIV; and
(5) the sigma-Delta modulator (SDM), configured to implement a fractional frequency division operation. A basic principle of this operation is to use the SDM to regularly control a frequency division ratio of the DIV so that a feedback frequency division ratio of the phase-locked loop regularly switches between two or more positive integer values, and finally obtains an average frequency division ratio as a required fractional frequency division value. For example, the frequency control word specified by the fractional frequency-division phase-locked loop is:
  FCW  =                    f        DCO                    f        REF              =          N      .      F      
In the foregoing formula, fDCO and fREF are a frequency of an oscillator output signal and a frequency of the reference clock respectively. A form of N.F is used in the foregoing formula to denote a fractional frequency division ratio, where N is an integer part of the frequency division ratio, and F is a fractional part of the frequency division ratio. By sending the frequency control word FCW into the SDM, a series of integral frequency division values in the vicinity of N can be obtained from an SDM output, that is:NDIV ∈ { . . . , N−2, N−1, N, N+1, N+2, . . . }
In the foregoing formula, NDIV is a frequency division control word output by the SDM for the feedback frequency divider, and N is an integer part of the frequency control word FCW) of the phase-locked loop. A specific value range of the NDIV depends on a design type of the SDM.
In the foregoing existing digital fractional frequency-division phase-locked loop, subject to control by the SDM, the frequency division ratio of the frequency divider DIV regularly changes among multiple integer values. Therefore, in a locked state of the phase-locked loop, the output CLK_DIV of the DIV is not a signal of a steady frequency. As shown in FIG. 2, it is assumed that an output frequency of the digital controlled oscillator DCO in the phase-locked loop is fDCO. Then its cycle is TDCO=1/fDCO. It is assumed that at the kth sampling point, the frequency division ratio of the DIV is NDIV[k], and at this point, an instantaneous cycle of the feedback clock CLK_DIV is:TDIV[k]=TDCO×NDIV[k]
It can be learned from the foregoing formula that because, in the locked state of the fractional frequency-division phased-locked loop, the NDIV value changes regularly subject to control by the SDM, the cycle of the feedback clock CLK_DIV changes accordingly. Corresponding to that, the cycle TREF of the reference clock CLK_REF is steady and unchanged. Therefore, as shown in FIG. 2, in a fractional frequency-division locked state, there is always a relatively large time domain deviation that changes in accordance with a particular rule between the reference clock CLK_REF and the feedback clock CLK_DIV. In FIG. 2, a time domain deviation at the kth sampling point is denoted by ΔTTDC[k]. In other words, in the existing digital fractional phase-locked loop, the TDC used to discriminate the time deviation between the CLK_REF and the CLK_DIV needs to be capable of precisely processing a given range of time domain inputs.
Another important constraint to design of the TDC is its resolution. In the digital phase-locked loop, a function of the TDC is to identify the time difference (or a phase difference) between the reference clock CLK_REF and the feedback clock CLK_DIV, and to convert the time difference into a digital signal at a particular resolution. Such operation may be described as:
            D      TDC        ⁡          [      k      ]        =      INT    ⁡          (                        Δ          ⁢                                          ⁢                      T            ⁡                          [              k              ]                                                R          TDC                    )      
In the foregoing formula, RTDC is a resolution of the TDC; the INT( ) function competes a rounding operation. As a special type of analog-to-digital converter, the resolution RTDC determines a level of quantization noise output by the TDC, and also determines an in-band phase noise level in the digital phase-locked loop. For a digital phase-locked loop applied to a cellular mobile communications system, a calculated TDC resolution is generally required to be RTDC<10 ps. For systems that have more stringent requirements on in-band phase noise, such as a wireless LAN, a higher requirement on the TDC resolution is imposed.
To sum up, two important factors need to be taken into consideration in design of the TDC: the input time domain range and the resolution. However, there is usually a tight trade-off between a range and an precision, and it is often difficult to meet the two dimensions at the same time. Due to a limitation of the structure of the TDC itself, a great challenge has been posed to the design of the TDC to meet the foregoing requirements. Therefore, how to reduce design difficulty of the TDC using a simple and effective means to ensure good convenience in design of a digital fractional frequency-division phase-locked loop system is an urgent issue to be resolved.